About
About Me
I’m an SoC, Fabric, and System architect with 25+ years of experience specializing in high-performance, scalable I/O and coherent fabrics (PCIe/CXL/UXI). I’ve spent my career at the boundary between architectural intent and silicon reality, defining fabric protocols, proving them correct, and making sure the RTL does what the spec says.
Architectural Philosophy
I believe in correct-by-construction silicon. That means:
- Data over intuition. Architectural decisions should be grounded in trace analysis, first-principles modeling, and exhaustive formal verification, not gut feel and hallway consensus.
- Machine-readable specifications. Prose specs accumulate ambiguity. I advocate for code-as-spec workflows (TLA+/PlusCal, XML/YAML/JSON, PlantUML) where the specification is executable, model-checkable, and precise enough for both humans and LLMs to consume without guesswork.
- Single source of truth. Every downstream artifact (human-readable docs, interactive tools, RTL, testbenches, etc.) should be generated from the same golden source. Spec-RTL drift is not a fact of life; it is a process failure.
- Spec-to-prompt precision. As AI-augmented design becomes the norm, the quality of the specification is the quality of the output. Ambiguity in the input is hallucination in the result.
Core Competencies
| Domain | Details |
|---|---|
| Interconnect Architecture | PCIe Gen6/7, CXL, UXI, SoC fabric design, caching & coherency |
| I/O Virtualization | VT-d, Intel VMD / Virtual Meta Device, device aggregation for rack-scale AI |
| Formal Methods | PlusCal/TLA+ modeling, TLC model checking, deadlock analysis, invariant proofs |
| Data-Driven Verification | Python trace modeling, PCIe/CXL trace analysis, bandwidth simulation |
| Methodology & Tooling | Machine-readable documentation, code-as-spec, interactive spec browsers |
| Technical Leadership | Specification governance, cross-functional alignment, mentorship |
Select Technical Wins
- GPU Interconnect Optimization: Led architectural discovery for PCIe P2P ordering enhancements. Identified and resolved a critical destination-change stall, enabling a ~2000% gain in nvbandwidth benchmarks for multi-agent GPU clusters while maintaining same-address ordering.
- Mesh Architecture Efficiency: Optimized mesh topology and protocol, reducing power consumption and alleviating oversubscription.
- Latency Reduction: Developed firmware-based custom multicast routing through the CPU, dramatically reducing latency, power, and platform cost for storage customers, leading to important design wins and customer retention.
- Virtual Meta Device: Re-architected the legacy Volume Management Device into a strategic scalability solution for server platforms, enabling virtualized storage and networking aggregation.
- 14 USPTO patent filings and 27 invention disclosures focused on interconnects, coherency, and virtualization.
Patent Portfolio
All of my granted patents and pending applications are publicly searchable through the USPTO Patent Public Search tool. Here’s the current list, as of today. Note that titles for granted patents appear twice, once as the application and once as granted.
| Patent / Publication No. | Title | Lead Inventor | Publication Date |
|---|---|---|---|
| US 2026/0228328 A1 | Device, Method and System to Protect Communications with a Resource of a Trusted Execution Environment | Shalini Sharma, et al. | 2026-08-06 |
| US 2026/0220060 A1 | Apparatus and Method for Efficient Management of High-Bandwidth IO Links | Filip Schmole, et al. | 2026-07-30 |
| US 2026/0187012 A1 | Methods for Performance-Optimal Tunneling of PCIe UIO/Flit-Mode Packets | Filip Schmole, et al. | 2026-07-02 |
| US 2026/0187234 A1 | Preventing Consumption of Incorrect Data Caused by Silent Drop of Trusted Write from Trusted Input/Output Devices to Private Memory of Trusted Virtual Machines | Shalini Sharma, et al. | 2026-07-02 |
| US 2026/0186839 A1 | Quality of Service Support for Input/Output and Other Agents | Andrew J. Herdrich, et al. | 2026-07-02 |
| US 12,650,940 B2 | Device Virtualization Techniques | Filip Schmole, et al. | 2026-06-09 |
| US 2025/0103397 A1 | Quality of Service Support for Input/Output and Other Agents | Andrew J. Herdrich, et al. | 2025-03-27 |
| US 12,248,561 B2 | Apparatus and Method for Role-Based Register Protection for TDX-IO | Vedvyas Shanbhogue, et al. | 2025-03-11 |
| US 2024/0419616 A1 | Memory Access for Multi-Chiplet System-in-Package | Kapil Sood, et al. | 2024-12-19 |
| US 2024/0291786 A1 | Management Control Message Routing | Janusz P. Jurski, et al. | 2024-08-29 |
| US 2024/0272911 A1 | Adjustment of Address Space Allocated to Firmware | Ramamurthy Krithivas, et al. | 2024-08-15 |
| US 2023/0136091 A1 | High-Performance Storage Infrastructure Offload | Kapil Karkra, et al. | 2023-05-04 |
| US 2023/0109533 A1 | Memory Usage Hints Between a Processor of a Server and a Network Interface Device | Daniel Biederman, et al. | 2023-04-06 |
| US 2023/0098288 A1 | Apparatus and Method for Role-Based Register Protection for TDX-IO | Vedvyas Shanbhogue, et al. | 2023-03-30 |
| US 2023/0077239 A1 | Device Virtualization Techniques | Filip Schmole, et al. | 2023-03-09 |
| US 11,216,396 B2 | Persistent Memory Write Semantics on PCIe with Existing TLP Definition | Mark A. Schmisseur, et al. | 2022-01-04 |
| US 2018/0089115 A1 | Persistent Memory Write Semantics on PCIe with Existing TLP Definition | Mark A. Schmisseur, et al. | 2018-03-29 |
Education
- M.S., Electrical and Computer Engineering | Georgia Institute of Technology
- Minor in Economics and Game Theory
- Teaching assistant in Microcotroller-Based Design
- B.S., Computer Engineering | Georgia Institute of Technology
- Teaching assistant in Calculus IV
Elsewhere
About This Site
Posts here cover hardware architecture, design, and verification, including the tools I build to make hardware design faster and more rigorous. Written for engineers who work in or adjacent to silicon design.